1. Field of the Invention
The present invention relates to a semiconductor memory which requires fresh operations to retain data written in its memory cells.
2. Description of the Related Art
Hand-held terminals such as cellular phones are growing in memory capacity requirement year by year. Under the circumstances, dynamic RAMs (hereinafter, referred to as DRAMs) have come to be used as the work memories of the cellular phones instead of conventional static RAMs (hereinafter, referred to as SRAMs). DRAMs are smaller than SRAMs in the numbers of devices that constitute the memory cells. DRAMs can thus be reduced in chip size, with lower chip cost than that of SRAMs.
Meanwhile, semiconductor memories to be mounted on cellular phones must be low in power consumption so as to allow prolonged use of the batteries. Unlike SRAMs, DRAMs require periodic refresh operations in order to retain data written in their memory cells. Consequently, when DRAMs are used as the work memories of cellular phones, data retention alone can consume power to exhaust the batteries even if the cellular phones are not in use.
In order to reduce the power consumption of the DRAMs during standby (in low power consumption mode), there have been developed partial refresh technology and twin cell technology.
According to the partial refresh technology; the number of memory cells to be refreshed is reduced by limiting the number of memory cells to retain data in a standby state. Reducing the memory cells to refresh can decrease the number of times of refresh, with a reduction in the power consumption during standby.
According to the twin cell technology, complementary data is stored into two memory cells (memory cell pair) which are connected to complementary bit lines, respectively. This doubles the charges retained in the memory cell pair. Since the two memory cells retain xe2x80x9cHxe2x80x9d data and xe2x80x9cLxe2x80x9d data, respectively, the refresh interval is determined by a longer one between the data retention times of xe2x80x9cHxe2x80x9d data and xe2x80x9cLxe2x80x9d data. That is, the worst data retention time is the sum of the characteristics of the two memory cells, not the characteristic of one single memory cell. On the contrary, in a single memory cell, the refresh interval is determined by a shorter one between the data retention times of xe2x80x9cHxe2x80x9d data and xe2x80x9cLxe2x80x9d data. As above, according to the twin cell technology, retaining data in two memory cells makes it possible to compensate a small leak path, if any, in one of the memory cells with the other memory cell.
In the partial refresh technology described above, to reduce the power consumption during the low power consumption mode requires that the data retention areas be small. As a result, the lower the power consumption, the smaller the memory capacity available for retention during the low power consumption mode.
In the twin cell technology, two memory cells are always used to retain a single bit of data not only in refresh operations but also in normal read operations and write operations. Storing a single bit hence requires a memory cell size twice as big as that of a single memory cell, which results in increasing chip cost. Consequently, in the cases of DRAMs to which the twin cell technology is applied, there is not much advantage in replacing the SRAMs mounted on cellular phones with the DRAMs.
It is an object of the present invention to reduce the power consumption of a semiconductor memory in low power consumption mode, the semiconductor memory having memory cells that require refresh operations.
According to one of the aspects of the semiconductor memory of the present invention, a partial area for retaining data in low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption in the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, a word line control circuit of the operation control circuit enables selection of a partial word line of word lines connected to the memory cells and disables selection of the other word lines, the partial word line being connected to the memory cell in the partial area. A sense amplifier control circuit of the operation control circuit keeps activating the sense amplifier during the low power consumption mode. Since the selection of the word lines other than in the partial area is disabled during the low power consumption mode, the sense amplifier keeps latching the data that is read from the memory cell. Consequently, data crash can be avoided during the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, the word line control circuit keeps selecting the partial word line during the low power consumption mode while the sense amplifier keeps latching the data. This simplifies the selecting/deselecting control of the word lines. That is, it is possible to reduce the scale of the control circuit for the word lines.
According to another aspect of the semiconductor memory of the present invention, a booster for supplying a boost voltage to the word lines stops its operation after the sense amplifier latches data at the start of the low power consumption mode. In returning from the low power consumption mode to the normal operation mode, the booster starts a boost operation again. Since the booster is operated only when the selecting operation of the word lines is necessary, the power consumption in the low power consumption mode can be reduced further.
According to another aspect of the semiconductor memory of the present invention, a mask circuit disables the selection of the word lines in response to a refresh control signal in the low power consumption mode. The semiconductor memory is thus prevented from malfunctioning.
According to another aspect of the semiconductor memory of the present invention, its operation mode shifts to the normal operation mode or the low power consumption mode in accordance with a chip enable signal for operating the semiconductor memory. Thus, shifting of the operation mode of the semiconductor memory can be made by simple control. This enables a simple configuration of the control circuit of a system implementing the semiconductor memory.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit selects first and second word lines simultaneously in second and subsequent refresh operations on each of the partial areas in the low power consumption mode. The operation control circuit can thus be configured simply.
According to another aspect of the semiconductor memory of the present invention, a plurality of partial areas for retaining data during low power consumption mode are each composed of a predetermined number of memory cells, of memory cells connected to a bit line. A refresh control circuit cyclically outputs a refresh control signal for refreshing the memory cells. An operation control circuit performs a read operation, a write operation, and a refresh operation on the memory cells. The partial areas each include a single first memory cell and at least a single second memory cell which are of the memory cells connected to the bit line.
At the start of the low power consumption mode, the operation control circuit performs a refresh operation on data retained in the first memory cell. The data is amplified by a sense amplifier and written to the first and second memory cells in the refresh operation. Consequently, the data in the first memory cell can be written to the second memory cell(s) with reliability. The operation control circuit subsequently refreshes the first and second memory cells simultaneously in response to the refresh control signal during the low power consumption mode. Since data retained in a single memory cell is retained by using a plurality of memory cells during the low power consumption mode, it is possible to extend the retention time over which the data can be retained. Consequently, the refresh intervals can be made longer in the low power consumption mode than in normal operations. A reduction in the frequency of refresh operations can reduce the power consumption in the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, in each of the partial areas, the first memory cell is connected to a first word line and the second memory cell(s) is/are connected to a second word line(s). A word line control circuit of the operation control circuit starts selection of the first word line earlier than selection of the second word line(s) in a first refresh operation on each of the partial areas in the low power consumption mode. This can prevent the data in the second memory cell(s) from being read first to destroy data retained in the first memory cell. That is, the semiconductor memory can be prevented from malfunctioning.
According to another aspect of the semiconductor memory of the present invention, the refresh control circuit outputs, in second and subsequent refresh operations in the low power consumption mode, the refresh control signal at intervals longer than in the normal operation mode. This can lower the refresh frequency in the low power consumption mode and reduce the power consumption.
According to another aspect of the semiconductor memory of the present invention, the refresh control circuit performs, in shifting from the low power consumption mode to the normal operation mode, a refresh operation only on the memory cell(s) on which a predetermined time elapses after a previous refresh operation has been performed. Performing a refresh operation on the necessary memory cell(s) allows a quick shifting from the low power consumption mode to the normal operation mode. Returning to the normal operation mode quickly can improve the operation efficiency of a system on which the semiconductor memory is mounted.
According to another aspect of the semiconductor memory of the present invention, the refresh control circuit outputs, in shifting from the low power consumption mode to the normal operation mode, the refresh control signal at intervals shorter than in the normal operation mode. This allows quick return from the low power consumption mode with the improved operation efficiency of a system on which the semiconductor memory is mounted.
According to another aspect of the semiconductor memory of the present invention, a switch circuit divides a bit line into first and second bit lines. A partial area is composed of a first memory cell out of memory cells, the first memory cell being connected to a first bit line lying on a side of the switch circuit closer to a sense amplifier. A refresh control circuit cyclically outputs a refresh control signal for refreshing the memory cells. A switch control circuit turns on the switch circuit in the normal operation mode, and turns off the same in the low power consumption mode. Since the bit line connected to the sense amplifier decreases in bit line capacity during the low power consumption mode, the sense amplifier can surely latch data retained in the first memory cell even if the signal quantity of the data is low. As a result, it is possible to lower the refresh frequency during the low power consumption mode, resulting in reducing the power consumption.
According to another aspect of the semiconductor memory of the present invention, a plurality of word lines to be selected in accordance with an address signal are connected to the memory cells, respectively. A word line control circuit selects any of the word lines in accordance with the address signal during the normal operation mode. The word line control circuit enables selection of a partial word line and disables selection of the other word lines during the low power consumption mode, the partial word line being one of the word lines and connected to the first memory cell in the partial area. Since the selection of the word lines other than in the partial area is disabled during the low power consumption mode, the sense amplifier keeps latching the data that is read from the memory cell through the selection of the partial word line. Consequently, data crash can be avoided during the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, first and second memory cells are connected to complementary bit lines, respectively. A sense amplifier is connected to the complementary bit lines. A refresh control circuit cyclically outputs a refresh control signal for refreshing the first and second memory cells. An operation control circuit operates either of the first and second memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation.
At the start of low power consumption mode, the operation control circuit makes the sense amplifier amplify data retained in the first memory cell, and writes it to the first and second memory cells (refresh operation). Consequently, the data in the first memory cell can be written to the second memory cell(s) with reliability. The operation control circuit subsequently refreshes the first and second memory cells simultaneously in response to the refresh control signal. The operation control circuit subsequently refreshes the first and second memory cells simultaneously in response to the refresh control signal during the low power consumption mode. Since data retained in a single memory cell is retained by using a plurality of memory cells during the low power consumption mode, it is possible to extend the retention time over which the data can be retained. Consequently, the refresh intervals can be made longer in the low power consumption mode than in normal operations. The lower frequency of refresh operations can reduce the power consumption in the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, the first memory cell is connected to a first word line and the second memory cell is connected to a second word line. The operation control circuit starts selection of the first word line earlier than selection of the second word line in a first refresh operation in the low power consumption mode. This can prevent the data in the second memory cell from being read first to destroy data retained in the first memory cell. That is, the semiconductor memory can be prevented from malfunctioning.
According to another aspect of the semiconductor memory of the present invention, the first and second word lines are adjacent to each other. This simplifies the circuit layout of a decoder and the like for selecting the first and second word lines.
According to another aspect of the semiconductor memory of the present invention, its operation mode shifts to the normal operation mode or the low power consumption mode in accordance with a command supplied through a command terminal. Thus, the operation mode of the semiconductor memory can be shifted by simple control. As a result, the control circuit of a system implementing the semiconductor memory can be configured simply.
According to another aspect of the semiconductor memory of the present invention, a first memory cell and a plurality of second memory cells are each connected to either of complementary bit lines. A sense amplifier is connected to the complementary bit lines. A refresh control circuit cyclically outputs a refresh control signal for refreshing the first and second memory cells.
An operation control circuit operates any of the first and second memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit performs at the start of low power consumption mode a refresh operation in which data retained in the first memory cell is amplified by the sense amplifier and written to the first and second memory cells, and subsequently refreshes the first and second memory cells simultaneously in response to the refresh control signal. Since data retained in the single memory cell is retained by using the first memory cell and the plurality of second memory cells during the low power consumption mode, it is possible to extend the retention time over which the data can be retained. Consequently, the frequency of refresh operations can be further reduced for a significant reduction in the power consumption during the low power consumption mode.
According to another aspect of the semiconductor memory of the present invention, the operation control circuit selects second word lines in succession after the selection of a first word line. It is therefore possible to disperse the consumption current of the control circuit that operates to select the word lines. This can reduce power supply noise and the like that occur with the selection of word lines.
According to another aspect of the semiconductor memory of the present invention, first and second memory cells are connected to complementary bit lines, respectively. A sense amplifier is connected to the complementary bit lines. For operation mode, the semiconductor memory has a first operation mode, a second operation mode, and a third operation mode.
In the first operation mode, at least either of a read operation and a write operation is performed on the first and second memory cells. In the second operation mode, data retained in the first memory cell is latched into a sense amplifier, and the latched data and inverted data thereof are written to the first and second memory cells, respectively. In the third operation mode, the data retained in the first memory cell and the inverted data retained in the second memory cell are latched into the sense amplifier, and the latched data and inverted data thereof are written to the first and second memory cells, respectively.
Since data retained in a single memory cell is retained by using a plurality of memory cells during the second operation mode, the retention time over which the data can be retained becomes longer in the third operation mode. Consequently, the frequency of data rewrite during the third operation mode decreases, which allows a reduction in the power consumption during low power consumption mode.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
FIG. 1 is a block diagram showing a first embodiment of the semiconductor memory of the present invention;
FIG. 2 is a circuit diagram showing the details of the PA control circuit and the word line control circuit shown in FIG. 1;
FIG. 3 is a circuit diagram showing the details of the word decoder shown in FIG. 1;
FIG. 4 is a block diagram showing the details of essential parts of the memory core shown in FIG. 1;
FIG. 5 is a timing chart showing the operation of the pseudo SRAM according to the first embodiment;
FIG. 6 is a block diagram showing a second embodiment of the semiconductor memory of the present invention;
FIG. 7 is a circuit diagram showing the details of the PA control circuit and the word line control circuit shown in FIG. 6;
FIG. 8 is a timing chart showing the operation of the pseudo SRAM according to the second embodiment;
FIG. 9 is a block diagram showing a third embodiment of the semiconductor memory of the present invention;
FIG. 10 is a circuit diagram showing the details of the refresh timer shown in FIG. 9;
FIG. 11 is a circuit diagram showing the details of the refresh register shown in FIG. 9;
FIG. 12 is a circuit diagram showing the details of the refresh register shown in FIG. 9;
FIG. 13 is a timing chart showing the operation of the refresh timer and the refresh register;
FIG. 14 is a circuit diagram showing the details of the word line control circuit shown in FIG. 9;
FIG. 15 is a circuit diagram showing the details of the word decoder shown in FIG. 9;
FIG. 16 is a block diagram showing the details of essential parts of the memory core shown in FIG. 9;
FIG. 17 is a timing chart showing the refresh operations of the pseudo SRAM according to the third embodiment;
FIG. 18 is a timing chart showing the operation of the pseudo SRAM according to the third embodiment;
FIG. 19 is a block diagram showing a fourth embodiment of the semiconductor memory of the present invention;
FIG. 20 is a circuit diagram showing the details of the refresh timer shown in FIG. 19;
FIG. 21 is a timing chart showing the operation of the pseudo SRAM according to the fourth embodiment;
FIG. 22 is a block diagram showing a fifth embodiment of the semiconductor memory of the present invention;
FIG. 23 is a circuit diagram showing the details of the refresh timer shown in FIG. 22;
FIG. 24 is a block diagram showing the details of essential parts of the memory core shown in FIG. 22;
FIG. 25 is a block diagram showing the details of essential parts of the memory core according to a sixth embodiment of the semiconductor memory of the present invention;
FIG. 26 is a circuit diagram showing the details of the sense amplifiers and column switches shown in FIG. 25;
FIG. 27 is a timing chart showing the operation of the pseudo SRAM according to the sixth embodiment;
FIG. 28 is a block diagram showing a seventh embodiment of the semiconductor memory of the present invention;
FIG. 29 is a block diagram showing the details of the operation mode control circuit shown in FIG. 28;
FIG. 30 is a timing chart showing the operation of the operation mode control circuit shown in FIG. 28;
FIG. 31 is a block diagram showing the details of the refresh timer shown in FIG. 28;
FIG. 32 is a timing chart showing the operation of the refresh timer and the refresh command generator according to the seventh embodiment;
FIG. 33 is a block diagram showing the details of the refresh address counter shown in FIG. 28;
FIG. 34 is a timing chart showing the operation of the resetting circuit shown in FIG. 33;
FIG. 35 is an explanatory diagram showing the operation of the refresh address counter shown in FIG. 33;
FIG. 36 is a block diagram showing the details of essential parts of the memory core shown in FIG. 28;
FIG. 37 is a circuit diagram showing the details of the 1/4 word decoder shown in FIG. 36;
FIG. 38 is a circuit diagram showing the details of the sense amplifiers and precharge circuits shown in FIG. 36;
FIG. 39 is a timing chart showing the operation of the sense amplifier control circuit and the precharge control circuit shown in FIG. 28;
FIG. 40 is a timing chart showing the operation of the seventh embodiment in normal operation mode;
FIG. 41 is a timing chart showing the operation of the seventh embodiment in common refresh mode;
FIG. 42 is a timing chart showing the operation of the seventh embodiment in partial refresh mode and concentrated refresh mode;
FIG. 43 is a timing chart showing the operation of the pseudo SRAM according to the seventh embodiment;
FIG. 44 is a block diagram showing an eighth embodiment of the semiconductor memory of the present invention;
FIG. 45 is a block diagram showing the details of the operation mode control circuit shown in FIG. 44;
FIG. 46 is a timing chart showing the operation of the operation mode control circuit shown in FIG. 44;
FIG. 47 is a block diagram showing the details of the refresh timer shown in FIG. 44;
FIG. 48 is a timing chart showing the operation of the refresh timer and the refresh command generator according to the eighth embodiment;
FIG. 49 is a block diagram showing the details of the refresh address counter shown in FIG. 44;
FIG. 50 is an explanatory diagram showing the operation of the refresh address counter shown in FIG. 49;
FIG. 51 is a block diagram showing the details of essential parts of the memory core shown in FIG. 44;
FIG. 52 is a circuit diagram showing the details of the 1/4 word decoder shown in FIG. 51;
FIG. 53 is a timing chart showing the operation of the sense amplifier control circuit and the precharge control circuit shown in FIG. 44;
FIG. 54 is a timing chart showing the operation of the eighth embodiment in normal operation mode;
FIG. 55 is a timing chart showing the operation of the eighth embodiment in common refresh mode;
FIG. 56 is a timing chart showing the operation of the eighth embodiment in partial refresh mode and concentrated refresh mode;
FIG. 57 is a block diagram showing another example of the memory core according to the fifth embodiment;
FIG. 58 is a timing chart showing another example of operation of the seventh embodiment in common refresh mode; and
FIG. 59 is a timing chart showing another example of operation of the eighth embodiment in partial refresh mode and concentrated refresh mode.